A synchronous design is a design whose outputs can only change in response to a logic transition of a predetermined signal, for example, a clock signal. Using a scan technique to test a synchronous design has been readily used by the prior art. In general, testing a synchronous design using a scan chain involves modifying the flip-flops within synchronous designs to have two additional inputs: (a) a scan input and (b) a scan enable input such that when the scan enable input is active, and a positive edge occurs on the clock input of the flip-flop, the logic value appearing on the scan input is stored in the flip-flop. This procedure is continued until all flip-flops are stored with their respective desired logic values. Upon the next clocking of the flip-flops, the stored logic values from the flip-flops are applied to combination logic to test such combination logic. The result of applying the logic values to the combinational logic is then captured by a subsequent clocking of the flip-flops wherein these results may also be shifted out via a scan out signal. As a result, because flip-flops are already present in synchronous designs, synchronous designs are desirable because they are easy to test.
On the other hand, an asynchronous design is one whose inputs and outputs can change at any time. A major advantage of asynchronous design over synchronous designs is that asynchronous designs dissipate substantially less power than synchronous designs. This is so because asynchronous circuits only dissipate power when actively computing instead of on every clock cycle. And therefore, less power is consumed because there is less switching. However, asynchronous designs have been avoided because they are difficult to implement and difficult to test. Moreover, since asynchronous designs do not inherently include flip-flops, the above described scan chain technique for synchronous designs is not applicable.
Hence, there exists a need for a technique and method for testing asynchronous designs.